1. Field of the Invention
The present invention relates to power-saving apparatus used for wireless communication systems, such as but not limited to wireless local area networks (WLAN), and in particular to a power-saving apparatus having a configurable analog-to-digital converter (ADC) whose output bits can be reduced for power-saving purposes.
2. Background
In wireless local area networks (WLAN) applications, the received signal strength can vary with a dynamic range up to 100 dB depending on the distance between a transmitter and a receiver. An Automatic Gain Control (AGC) circuitry has been widely used in WLAN receivers to optimize its range performance. Typically a pair of 8-10 bit analog-to-digital converters are implemented to have the required resolution to decode the highest data rate, which has the largest peak-to-average-ratio (PAR), in the presence of severe multipath and/or adjacent channel interference from other WLAN or Bluetooth users nearby. However, this worst-case-scenario design costs the hardware to consume more power than required in practical operations. For example, if an 802.11 receiver is in close vicinity to an 802.11 access-point, a pair of ADC's each with a smaller number of bits will be sufficient to achieve the same level of system performance. In this case, the ADC power saving can be significant. As an example, one can easily achieve a 20% or more ADC power-saving if a 10-bit pipelined ADC design can be configured as an 8-bit ADC on a per packet basis. While first implemented in the early 2000's, a typical WLAN transceiver consists of three chips, one power amplifier (PA) chip, one RF transceiver chip, and one integrated base-band (BB) and Medium Access Control (MAC) chip. To further lower down the total cost of a WLAN transceiver, integration of the PA function into the RF transceiver chip has been achieved. Lately, a single-chip WLAN transceiver implementation has really become popular, although some still prefer to use an external PA. FIG. 1 shows a functional block diagram for a wireless transceiver, which includes a direct-conversion (also known as zero-IF) receiver, for WLAN applications. At the highest level, it contains four functional blocks: an antenna 11, an antenna switch 12, a transmitter 20 and a receiver 10.
A detailed functional block diagram for the receiver 10 is also shown in FIG. 1. The receiver 10 contains two major functional blocks: a RF receiver 30 and a base-band demodulator 40. As is shown in FIG. 1, a typical RF receiver 30 consists of a first stage of low noise amplifier (LNA) 13a and a second stage of LNA 13b, a pair of mixers 14a and 14b, a pair of channel selection filters 17a and 17b, and a pair of multiple stages of Variable Gain Amplifiers (VGA's) 18a and 18b. 
The first stage of LNA 13a and the second stage of LNA 13b are used to amplify a weak received signal with minimum distortion. In other words, the first stage of LNA 13a and the second stage of LNA 13b are used to enhance the sensitivity of the receiver. To provide the best sensitivity, an LNA stage typically provides a gain over 15 dB and a Noise Figure (NF) between 1.5 to 2.5 dB.
In the presence of a very strong signal, it is usually desirable to turn off some or all LNA stages if multiple LNA stages are used. The output of the first stage of LNA 13a and the second stage of LNA 13b is connected to a pair of mixers 14a and 14b. To keep the fidelity of the received signal in a direct-conversion receiver, two mixers are required to provide an in-phase and a quadrature phase base-band signals. One mixer 14a takes the carrier generated by the synthesizer 16 as one input and the output of the second stage LNA 13b as another input to convert the received Radio Frequency (RF) signal to a base-band In-phase signal (also known as I-channel) as its output. The other mixer 14b uses a 90-degree phase-shifted carrier 15 as one input and the output of the second stage of LNA 13b as another input to convert the received RF signal to a baseband Quadrature-phase signal (also known as Q-channel) as its output. In what follows, the received in-phase and quadrature signals will be referred as I-channel and Q-channel signals, respectively. From now on, the processing of both I-channel and Q-channel signals is essentially the same. So it is sufficient to describe the processing of the I-channel signal.
For the I-channel signal, a low-pass filter 17a is applied to the corresponding mixer output to filter out the adjacent channel interferences and the unwanted mixer output at twice the received RF signal frequency. The I-channel filter 17a output is connected to the variable gain amplifiers (VGA) 18a for gain adjustment. In this diagram, each VGA 18a contains two Variable Gain Amplifier stages 19a and 19b with their gain controlled by the AGC control signals (as shown in FIG. 1) generated by AGC 22. As its name shows, each VGA stage 19a or 19b allows one to adjust its control voltage for providing variable gain to its input signal. Typically, a VGA stage has a dynamic range of 20 to 30 dB with a gain adjustment step of 1 or 2 dB. To achieve a wider receiver dynamic range, 3 or more VGA stages may be implemented. The output of the VGA 18a is connected to an analog to digital converter (ADC) 21a of the base-band demodulator 40. The ADC 21a digitizes and coverts its input signal to the digitized I-channel samples for further processing of the received signal by the base-band demodulator processor 23 in digital domain. Detail operations will be presented later.
To fully utilize the dynamic range of an ADC, the input to an ADC needs to be maintained at or close to an optimal level. This is achieved by the receive signal strength indicator (RSSI) measurement and automatic gain control (AGC) 22 circuitry. The RSSI measurement and AGC 22 circuitry, most commonly implemented in the base-band demodulator receiver 40, estimates the received signal strength PR based on the digitized I and Q samples, and then generates VGA and LNA control signals as its outputs, with a VGA control signal for VGA 18a/18b gain setting and an LNA control signal for the ON/OFF states control of the first stage of LNA 13a and the second stage of LNA 13b. 
It was mentioned above that it is usually desirable to turn off some or all stages of the LNA's if multiple LNA stages are used in the presence of a very strong signal. The AGC function above serves to generate control signals for LNA stages ON/OFF states and VGA's gain setting, based on the estimated receive signal power, PR. Typically, it takes a small amount of time, TLNA to completely switch on or off an LNA stage. During this time period, the AGC block usually stops estimating the received signal power until the LNA stage on/off switch has been completed. Therefore, if an ADC circuitry can be designed to simultaneously switch part of its circuitry off while an LNA stage is being switch off, and vice versa, then one can have an ADC with adaptive output bits to properly save the ADC operating power. The crux resides in the fact that the ADC switch time, TADC, is usually smaller than the LNA switching time, TLNA. In this case, both the LNA switch and ADC switch can be accomplished without slowing down the operation of AGC. Otherwise, the AGC function could be stopped for a little longer time equal to TADC, greater than TLNA when a LNA is switched off. This is not desirable since the whole AGC process must be done within a very limited time in the beginning of a packet to tackle a possible 100 dB dynamic received-power range.
In FIG. 2, a functional block diagram for a traditional 10-bit pipelined ADC implementation 3 is shown. One can consider that there is an N=10 pipelined ADC implementation for N-bit ADC 21a or 21b in FIG. 1. This specific implementation has 5 Stages 31-35. With each Stage 31-35 serving to output 2 bits, an analog input signal is digitalized to a 10-bit output sample: (b9, b8, b7, b6, b5, b4, b3, b2, b1, b0), with b9 being the most significant bit, and b0 being the least significant bit.
U.S. Pat. No. 7,212,795, issued to Der-Zheng Liu et al. entitled “Automatic gain control and antenna selection method for a radio communication system” discloses an automatic gain control and antenna selection method used in a receiver of a radio communication system. This patent application is focused on the received signal power is estimated by digital signal processing after analog-to-digital conversion in the system, in order to adjust the gain of the front end analog signal until the magnitude of the analog signal is adjusted to an optimum range of the digital signal processing. In addition, the ADC is utilized to estimate the signal power as the basis of the antenna selection.
However, the above disclosure does not effectively control the N-bit ADCs in the baseband demodulator, which can not save the power significantly. According to the above discussions, it need a method and apparatus to overcome the disadvantage of the prior art.